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NJU8402
PRELIMINARY
DIGITAL TO ANALOG CONVERTER FOR STEREO AUDIO
s GENERAL DESCRIPTION
The NJU8402 is a 16-bit delta-sigma Digital-to-Analog Converter for stereo audio. It consists of Serial Audio Data Interface, Digital Interpolation Filter, Modulator, SC LPF, Buffer Amp, System Controller for status control. It operates on single +5V power supply. Furthermore, it accepts 16-bit input audio data length or 18-bit, and supports I2S serial data format and LSB justified. Therefore, the NJU8402 is suitable for CD, MD, DAT and other digital audio applications.
s PACKAGE OUTLINE
NJU8402D
NJU8402M
s FEATURES
q q q q q q q q type 1bit stereo DAC Sample Rate ( fs ) : 50kHz ( Maximum ) Signal-to-Noise Ratio : 94dB Input Audio Data Length : 16bits or 18bits Single ended Analog Output Internal SC type Low Pass Filter Operating Voltage +5V 5% Package Outline DIP16 / DMP16
s PIN CONFIGURATION
VDD MCKI SCK DATA REQ AOUTL VCOML AVDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VSS BCLK LRCK DIN RST AOUTR VCOM AVSS
s BLOCK DIAGRAM
DIN BCLK LRCK Serial Audio Data Interface
Digital Interpolation Filter
Modulator Modulator
SC LPF SC LPF
LPF
AOUTL VCOML
LPF
AOUTR VCOMR
System Controller
SCK REQ MCKI RST DATA
VSS
AVDD
AVSS
VDD
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NJU8402
s TERMINAL DESCRIPTION
PIN No. 1 16 8 9 2 13 14 15 SYMBOL VDD VSS AVDD AVSS MCKI DIN LRCK BCLK INPUT /OUTPUT I I I I FUNCTION Digital Power Supply, +5V Digital GND, 0V Analog Power Supply, +5V Analog GND, 0V Master Clock Input Terminal The input signal frequency is 256 times or 384 times of fs. Serial Audio Data Input Terminal L/R Channel Clock Input Terminal This clock must synchronize with MCKI. Audio Serial Data Clock Input Terminal This clock must synchronize with MCKI. Control Register Serial Data Sift Clock Input Terminal Control register leads the control data synchronizing the rising edge of SCK signal. When the control register is not used, the state of SCK terminal has to keep level "H". Control Register Serial Data Input Terminal Input data sets various functions. When the control register is not used, the state of DATA terminal has to keep level "H". Control Register Serial Data Request Input Terminal The control data are latched in the control register at the rising edge of REQ signal. When the control register is not used, the state of REQ terminal has to keep level "H". Reset "L" level signal into reset terminal initializes the system. Left channel Analog Signal Common Terminal for Connecting Smooth Capacitor A chemical capacitor should be connected between this terminal and AVSS for stabilizing. Right Channel Analog Signal Common Terminal for Connecting Smooth Capacitor A chemical capacitor should be connected between this terminal and AVSS for stabilizing. L-Channel Analog Signal Output Terminal R-Channel Analog Signal Output Terminal
3
SCK
I
4
DATA
I
5
REQ
I
12 7
RST VCOML
I O O
10 6 11
VCOMR AOUTL AOUTR
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NJU8402
s FUNCTION DESCRIPTION
(1-1) Analog Audio Signal Output Analog signal output is biased in the chip and the maximum amplitude is 0.56 x AVDD. The internal switched capacitor Low Pass Filter is so effective that the external Low Pass Filters are required only 2pole LPF or 3-pole.
(1-2) Serial Data Interface DIN (Data Input), BCLK (Bit Clock) and LRCK (L/R Clock) are the serial data interface terminals. BCLK is the bit clock of audio data and IO data are leaded at raising edge of the BCLK. The signal into LRCK terminal represents the signal for distinguishing between Lch and Rch, and the signal for starting data. The frequency of LRCK is sampling rate of system ( fs ). The MCIK must be synchronized with LRCK and is 256 times or 384 of fs. The serial data format is complement of 2, MSB-first and compatible with I2S serial data protocol or LSB justified. This serial data format is set by the control register. LRCK Left Right Channel
BCLK
DIN
151413
10
151413
10
I2S serial data format
LRCK
Left
Right Channel
BCLK
DIN
0
1514
210
1514
210
LSB justified serial data format
(1-3) System Clock System Clock into the MCIK terminal must be 256 times or 384 times of fs and synchronizing with LRCK. This frequency is set by the control register.
(1-4) Reset The external reset is the asynchronous reset. Reset is released at the falling edge at LRCK. Reset by command is synchronous which operates as same as the external reset function.
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NJU8402
(1-5) Control Register The Control Register controls NJU8402 operation using the serial interface. The SCK terminal is the data sift clock, the REQ terminal is data request signal, the DATA terminal is the serial data input. The control data is loaded into the sift register at rising edge of SCK, then it is latched at the rising edge of REQ. The least 8-bit data, which order is MSB first, is valid for control.
REQ
SCK
DATA
B7
B6
B5
B4
B3
B2
B1
B0
CONTROL PORT TIMING CHART
*
Serial Data Format B7 0 0 B6 0 0 B5 0 0 B4 0 1 B3 B2 DIF1 B1 DIF0 B0 CLKR RST (: Don't Care)
*1 Don't input commands except this table.
0 System Clock Data Length Format Reset CLKR DIF0 DIF1 RST 256fs 16 I2S Normal
1 384fs 18 LSB Justified Reset
Default 0 0 0 *2
*2 The level becomes 0 after initial setting.
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NJU8402
s ABSOLUTE MAXIMUM RATING
(VSS=AVSS=0V) PARAMETER DIGITAL Power Supply ANALOG VDD - AVDD Input Voltage Operating Temperature Storage Temperature Power Consumption SYMBOL VDD AVDD VAVD VIN Ta Tstg PD CONDITIONS -0.3 to+7.0 -0.3 to +7.0 VDD - AVDD<0.2 -0.3 to VDD + 0.3 -30 to +80 -40 to +125 500DIP16 200(DMP16) UNIT V V V V C C mW
s RECOMMENDATION OPERATION CONDITION
(VSS=AVSS=0V) PARAMETER Power Supply DIGITAL ANALOG SYMBOL VDD AVDD MIN. 4.75 4.75 CONDITIONS TYP. 5.0 5.0 MAX. 5.25 5.25 UNIT V V
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NJU8402
s ELECTRICAL CHARACTERISTICS * ANALOG AC CHARACTERISTICS
(The case without the report Ta=25,VDD=AVDD=5.0V,fs=44.1kHz, Input Signal Frequency=1kHz, Input Signal Level=Full Scale,MCKI=256fs,Bandwidth=22Hz to 20kHz) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Resolution 16 bit S/N S/N EIAJ, A-weight 90 94 dB Dynamic Range DR EIAJ, A-weight 94 dB THD+N THD+N Output 0dB dB -88 -82 Channel Separation EIAJ(1kHz) 90 dB Differential Gain 0.1 0.3 dB Between Channels Gain Drift 100 ppm/C Maximum Output Voltage 0.55xAVDD 0.57xAVDD 0.59xAVDD VPP Bias V 0.50xAVDD Output Load Resistance Output Load Capacitance 10 300 k pF
BLOCK DIAGRAM FOR TESTING ANALOG AC CHARACTERISTICS
Digital Data
Digital Audio Interface Receiver Chip
NJU8402
Two-pole LPF
Filters
THD Meter
NJU8402 Evaluation Board Two-pole LPF Filters
Audio Analyzer
: fc=25kHz ( refer APPLICATION CIRCUITS ) : 22Hz HPF 20kHz Ten-pole LPF ( A-Weighting Filter is on at measuring S/N and Dynamic Range
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NJU8402
* DIGITAL INTERPOLATION FILTER CHARACTERISTICS
(The case without the report. Ta=25,VDD=AVDD=5.0V,fs=44.1kHz) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Band Pass PB 0.02 20.0 kHz Rejection Band SB 24.10 kHz Rejection Band Quantity SA 50 dB Note :Band Pass and Rejection Band are proportioned to fs. PB=0.4535xfs,SB=0.5465xfs
* DIGITAL ANALOG LOW PASS FILTER CHARACTERISTIC
PARAMETER Frequency Response (The case without the report. Ta=25,VDD=AVDD=5.0V,fs=44.1kHz) SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE FR dB 22Hz20kHz 0.2
* POWER CHARACTERISTICS
PARAMETER Supply Voltage VDD Supply Current AVDD (The case without the report Ta=25,VDD=AVDD=5.0V,fs=44.1kHz) SYMBOL CONDITIONS MIN. TYP. MAX UNIT NOTE VDD, AVDD 4.75 5.0 5.25 V IDD No signal 12 14 mA AIDD No signal 10 18 mA
* DIGITAL DC CHARACTERISTICS
PARAMETER Digital Input Voltage Input Leakage Current SYMBOL VIH VIL ILK CONDITIONS (The case without the report Ta=25,VDD=AVDD=5.0V) MIN TYP MAX UNIT NOTE VDD 0.7 VDD V 0.3 VDD V 1 A
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NJU8402
* DIGITAL AC CHARACTERISTICS
(The case without the report Ta=25,VDD=AVDD=5.0V) Master Clock & Reset PARAMETER Frequency MCKI Pulse Width High-Level Pulse Width Low-Level Reset Low Level Width
SYMBOL CONDITIONS 256fs fMCKI 386fs tMCKH tMCKL tRST
MIN. 1.024 9.216 20 20 1
TYP.
MAX. 12.8 19.2
UNIT MHz MHz ns ns ns
NOTE
Digital Audio Signal Interface PARAMETER Audio DAC Sampling Late Audio Data Setup Time Audio Data Hold Time BLCK Period BLCK Pulse Time "H" BLCK Pulse Time "L" BCLK Rise to LRCK Edge LRCK Edge to BCLK Rise
SYMBOL CONDITIONS fs tDS tDH tBCLK tBCKH tBCKL tBLR tLRB
MIN. 24 50 50 1/(128fs) 20 20 40 40
TYP.
MAX. 50
UNIT kHz ns ns ns ns ns ns ns
NOTE
Control Register Interface PARAMETER SCK Period SCK Pulse Time "H" SCK Pulse Time "L" Control Data Setup Time Control Data Hold Time REQ Pulse Time "H" SCK Data Setup Time REQ Hold Time
SYMBOL CONDITIONS tSCK tSCH tSCL tDAS tDAH tREH tRQS tRQH
MIN. 2 0.8 0.8 0.8 0.8 1.6 0.8 0.8
TYP.
MAX.
UNIT ns ns ns ns ns ns ns ns
NOTE
Input Signal Rise and Fall Time PARAMETER Input Signal Rise Time Input Signal Fall Time
SYMBOL CONDITIONS tUP tDN
MIN.
TYP.
MAX. 100 100
UNIT ns ns
NOTE
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NJU8402
* TIMING CHART
Master Clock & Reset MCKI tMCKL RSTX tMCKH tRST 1/fMCKI
Digital Audio Signal Interface
tBCLK
BCLK INPUT tBLR tLRB tBCKL tBCKH
LRCK INPUT tDS tDH
DIN
Control Register Interface tRQS REQ tSCH SCK tSCK DATA tDAS tDAH Input Signal Rise and Fall Time 90% 10% tUP tDN tSCL
tLRD0 tRQH tREH
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NJU8402
s APPLICATION CIRCUITS
Two-pole LPF
+12 10uF 0.1uF
20k 2.2uF 20k DIN Digital Audio Data (16 or 18 bits) AOUTL 680pF LRCK OP:NJM5532 VCOML 10uF
150pF 20k OP 10uF 0.1uF
BCLK
-12V
NJU8402
AOUTR SCK VCOMR 10uF AVDD(+5V) AVDD MCK & 8 bits Serial Control 10uF MCKI AVSS VDD (+5V) RSTX VDD 10uF VSS DATA VSS (Digital GND) 0.1uF AVSS (Analog GND) 0.1uF Two-pole LPF
REQ
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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